You can have more than one DSP operation running and operations can feed data from one to the next in streaming mode with no buffering. You program InferX using Simulink at a higher level. Our team writes the Softlogic that executes the DSP operations on InferX. We have a team who has been writing high speed “Softlogic” (Verilog/RTL code) for years. Table 1: InferX DSP throughput, TSMC N5 – note performance increases linearly with more tiles. Reconfiguration happens in microseconds.Īnd InferX can execute DSP operations with very high throughput as shown in the following table where we use as an example 5nm and show throughput using 1 tile and 8 tiles (we can deliver arrays, with AXI bus interface, for any rectangular arrangement of tiles): Unlike fully hardwired solutions, having eFPGA means you can always adapt to changing models.Ĭustomers tell us that InferX is not much bigger than a fully hardwired DSP circuit that only does one task, but InferX can be reconfigured on the fly to do any DSP function. eFPGA can also be used to implement new operators, which pop up all the time as models continue to evolve.

But it is 100% reconfigurable because the 16 tensor processors are in a reconfigurable interconnect, allowing the arrangement of tensor processors to be optimized for each function, and eFPGA is used as the control plane to manage operation at high speed with fine granularity. InferX is 80% hardwired: almost all of the datapath is hardwired. InferX DSP: 100% programmable, 80% hardwired What customers want is fully reconfigurable DSP IP that is as close as possible to the area and power of a hardwired design. VLIW based DSP IP is not as fast as FPGA but costs less and uses less power but has a large area/power premium compared to hardwired. What we hear from customers is that there is a growing need for very fast and very flexible DSP, which hardwired solutions can’t address.Īnd that the fastest solutions are FPGAs, but they are big, high power and high cost: the customers are only using the MAC/math portion of the FPGA but having to pay for the power and cost of the rest of the unused logic. Use FPGAs with DSP MACs or math engines.Hardwire your function – zero flexibility.Today if you want high performance DSP you have three choices:

Hard wired server design